The embodiments of the present invention relate to processing systems that have two or more processors, such as two or more processor cores, and particularly relate to those processing systems in which one of the processors or processor cores can be executing instructions or otherwise operating while another processor or processor core can be in a low power state such as a low power sleep state in which processing is reduced or totally eliminated.
A common chain of events in modern computing operating systems can start with a hardware interrupt that causes a first processor to wake up (from a low power sleep state) and execute an interrupt handler. This in turn causes a thread to be made runnable to which the scheduler responds by executing that thread. In multi-processor systems, the operating system must make choices about when to wake up additional processors, particularly when the first processor receives a new interrupt while it is already processing an interrupt and while a second processor is in a low power sleep state. If the first processor chooses not to wake up the second (or other additional) processors, then the execution of the newly runnable thread will be delayed while the first processor continues processing any interrupts. This adds scheduling latency to the newly runnable thread, but potentially avoids waking up the second processor that may have nothing to do. Most of the time this added latency is short, but in a busy system, additional interrupts could delay the thread significantly. If the operating system chooses to wake up the second processor or additional processor as soon as the thread is made runnable, the thread will see minimal scheduling latency. However, if the interrupt processing on the first processor completes quickly, the original processor (the first processor) will then be left with nothing to do and be put back to sleep. In effect, two processors would be woken up to do one processor's amount of work. Both of these strategies are used in modern operating systems, depending on the expected workload and desired balance between performance and power efficiency.